Integrated circuits are typically manufactured using a photomask called a reticle which may include multiple instances of the same integrated circuit chip in which case the reticle may be called a multi-chip reticle. The lithographic and other fabrication process used to transfer the pattern on the reticle into a photoresist layer and thence to underlying physical layers on a semiconductor substrate may not be uniform across the entire field of the reticle. Presently, in order to account for this non-uniformity, shapes processing procedures which will collectively be referred to here as reticle correction are performed to modify the patterns on the reticle so that the physical patterns created on the semiconductor substrate are closer to the design intent. Reticle correction is performed using one of two approaches. In the first approach, reticle correction is applied to every instance of the integrated circuit chip in the reticle design dataset. In this way the pattern modifications can be made to account for the location of shapes within the entire reticle. Since these techniques can take many days to weeks to run, even on the most powerful computer systems, it is often not cost effective to do so. In the second approach, the reticle correction is performed once to the chip design, and the modified pattern information is then duplicated in all instances of the chip on the reticle. This reduces the runtime requirements but does not allow for separate reticle correction modifications to be made to corresponding shapes in different instances of the chip on the reticle, and thus there is often a range in performance between integrated circuit chips formed from different instances of the integrated circuit chip on the reticle.
Electrical characteristics of structures in an integrated circuit chip such as resistance, capacitance, and transistor channel length, are normally determined from the set of shapes to be used to manufacture the chip using a shapes processing procedure known as electrical extraction. The non-uniformity across the reticle field in the lithographic and other fabrication processes may cause a manufactured pattern or structure created on the semiconductor substrate in different integrated circuit chips of a multi-chip reticle to differ, and hence to have different electrical characteristics. A conventional method of accounting for these varying electrical characteristics in electrical extraction is to report a range of values for a parameter (e.g., an electrical resistance) which bound the minimum and maximum values that the parameter have at any location within the reticle field. Because the shapes used to generate certain structures will occur only within limited areas of the reticle field, an electrical extraction process which reports such a wide range of parameter values will be pessimistic. This pessimism may cause an under-prediction of the performance of the integrated circuit, or may cause expenditure of unnecessary design effort, circuit area, or power to ensure that the integrated circuit will operate as desired.
Therefore, what is needed is a more cost-effective method for performing shapes processing procedures and for applying reticle enhancement and electrical extraction techniques, to instances of the integrated circuit on a multi-chip reticle.